Delta Sigma (or Sigma Delta) converters are a well-known type of converter circuit providing a high resolution output with a low implementation cost.
An example of a known 2nd order Delta Sigma converter is illustrated in FIG. 1. An analogue input signal 10 is received, and a feedback error signal subtracted 12 from the input. The resulting difference value is integrated (or summed) in first integrator 14. The error signal is then subtracted 16 from the output of the first integrator 14, with the resulting difference being the input for a second integrator 18. The output of the second integrator 18 is sent to a comparator 20 which is operable to output a HIGH or LOW value, depending on the value of the input signal. The comparator 20 output is coupled to the input of a latch 22 driven by a system clock 24. The latch 22 outputs a single bit stream which is the output 26 of the Delta Sigma converter, and which may be used by appropriate output hardware (not shown) to produce an output value in the appropriate range required. The single bit stream is also used as the input to a 1 bit DAC 28, the output of which is used as the feedback signal for the two subtraction operations 12 and 16.
A corresponding feedback signal for an arbitrary input signal is shown in FIG. 2. It can be seen that the feedback signal output by the DAC 28 follows the clock 24 in timing and pulse width.
It is an object of the invention to provide a Delta Sigma system having improved noise characteristics, performance, and flexibility of implementation